The driver circuit is a circuit of which basic operations are to output signals at high-level or low-level in accordance with inputs. In a recent driver circuit, an output impedance (DC characteristics) is defined and an output slew rate (AC characteristics) is defined.
FIG. 9 is a view illustrating a configuration of a driver circuit. A driver circuit 210 includes a PMOS output stage 220P, an NMOS output stage 220N, pre-buffer groups 230P, 230N driving the PMOS output stage 220P and the NMOS output stage 220N, and a slew rate control part (current source circuit) 240. Besides, an input signal IN, an impedance code PMIC for PMOS and an impedance code NMIC for NMOS to control the output impedance, and a slew rate control signal SRCTL to control the output slew rate are supplied to the driver circuit 210 from a logic part 250. Besides, the other control signals SIG are supplied from the logic part 250 to the driver circuit 210. Note that the impedance codes PMIC, NMIC are generated by an impedance code generation part 260 having the same configuration as the output stages 220P, 220N.
The PMOS output stage 220P includes plural P-channel type transistors as output transistors. In each of the P-channel type transistors, a source is connected to a power supply line of a voltage VDDH, a drain is connected to an output terminal of an output signal OUT via a resistor ROP. Besides, the NMOS output stage 220N includes plural N-channel type transistors as the output transistors. In each of the N-channel type transistors, a source is connected to a power supply line of a reference potential VSS, a drain is connected to the output terminal of the output signal OUT via a resistor RON. When high-level is output, a gate voltage of the output transistor of the PMOS output stage 220P is set at a voltage VSS to set in ON state, and a gate voltage of the output transistor of the NMOS output stage 220N is set at the voltage VSS to set in OFF state. When low-level is output, the gate voltage of the output transistor of the PMOS output stage 220P is set at the voltage VDDH to set in OFF state, and the gate voltage of the output transistor of the NMOS output stage 220N is set at the voltage VDDH to set in ON state.
The output transistors of the PMOS output stage 220P are controlled by pre-buffers 230P-1, 230P-2, . . . , 230P-n provided to correspond to each of them. The output transistors of the NMOS output stage 220N are controlled by pre-buffers 230N-1, 230N-2, . . . , 230N-n provided to correspond to each of them.
The respective pre-buffers 230P-i, 230N-i (“i”=a natural number of one to “n”) include ON/OFF control parts 231P, 231N objected to adjust the output impedance, and gate driving parts 232P, 232N objected to adjust the output slew rate. The ON/OFF control parts 231P, 231N adjust the number of output transistors of which ON/OFF control is to be performed in accordance with the input signal IN at the PMOS output stage 220P and the NMOS output stage 220N based on the impedance codes PMIC, NMIC to adjust the output impedance. Driving abilities of the gate driving parts 232P, 232N are controlled by bias voltages BIASP, BIASN supplied from the slew rate control part 240, and the gate driving parts 232P, 232N drive the output transistors of the PMOS output stage 220P and the NMOS output stage 220N.
The slew rate control part 240 includes an internal constant-current source 241 and a bias voltage generation part 242. The slew rate control part 240 generates and outputs the bias voltages BIASP, BIASN in accordance with the slew rate control signal SRCTL. The internal constant-current source 241 includes a resistor R201 and an N-channel type transistor NT201 connected between a power supply line of the voltage VDDH and a power supply line of the reference potential VSS, and generates an input current. A gate voltage CMI for the N-channel type transistor in accordance with the input current is supplied to the bias voltage generation part 242. The bias voltage generation part 242 includes an N-channel type transistor which is current-mirror connected to the N-channel type transistor NT201 of the internal constant-current source 241. The bias voltage generation part 242 performs a current-voltage conversion of an output current in accordance with the input current obtained by changing a current-mirror ratio in accordance with the slew rate control signal SRCTL, and generates and outputs the bias voltages BIASP, BIASN.
An art is proposed in which plural transistors are connected in parallel, and a desired resistance value is enabled by turning ON/OFF the transistors by means of a digital control (for example, refer to Patent Documents 1, 2). In Patent Document 1, it is described in which a level detection by using a reference resistance is performed, and a resistance value equivalent to the reference resistance is generated by the plural transistors connected in parallel. Besides, a driver circuit is proposed in which driving ability is made adjustable by selecting and driving plural driving transistors connected in parallel in accordance with a control signal (for example, refer to Patent Document 3).
[Patent Document 1] Japanese Laid-open Patent Publication No. 2006-66833
[Patent Document 2] Japanese Laid-open Patent Publication No. 2006-42136
[Patent Document 3] Japanese Laid-open Patent Publication No. 2006-42137
In the driver circuit 210 illustrated in FIG. 9, the output slew rate is controlled by the bias voltages BIASP, BIASN in accordance with the slew rate control signal SRCTL supplied to the gate driving parts 232P, 232N of the pre-buffers 230P-i, 230N-i. However, there is a case when a desired slew rate is not obtained caused by variations of the bias voltages BIASP, BIASN resulting from manufacturing variability of the slew rate control part 240, in particular, the internal constant-current source 241. Besides, there is also a case when the desired slew rate is not obtained caused by manufacturing variability of the gate driving parts 232P, 232N held by the pre-buffers 203P-i, 230N-i.